The present invention relates generally to integrated circuit ADCs (analog to digital converters), and particularly to ADC circuits and methods for correcting the gain of an ADC with minimum circuit complexity, a minimum amount of integrated circuit chip area, and a minimum amount of time required in addition to the basic ADC conversion time in order to accomplish the gain error correction.
Every ADC has gain error. There are two basic ways to correct the ADC gain error, namely analog correction and digital correction. One analog gain error correction technique is trimming of the reference voltage. That controls the transfer function of the converter so as to achieve whatever correction is needed for its gain. Another analog ADC gain correction technique is scaling the ratios of the sampling capacitors of the integration stage of the ADC. However, the known analog techniques for correcting ADC gain error require increased amounts of integrated circuit die area, and they typically require use of costly laser trimming techniques. Furthermore, the gain correction accuracy which can be achieved using analog ADC gain error correction techniques is less than can be achieved using digital ADC gain error correction techniques. Also, digital gain error correction techniques are easier to implement during final integrated circuit testing procedures than the analog gain error correction techniques.
Several digital methods for trimming ADC gain error have been employed. FIG. 1 illustrates a prior art delta-sigma ADC 20A which includes an integrator 17, the (−) output 27A of which is coupled to the (−) input of a window comparator 30. The (+) output 27B of integrator 17 is coupled to the (+) input of window comparator 30. Window comparator 30 may be composed of two or more conventional comparators which receive various threshold voltages VTH on the various conductors of window comparator threshold bus 29, respectively. An input signal voltage Vin=Vin+−Vin− is coupled between plates of sampling capacitors 23A and 23B, the other plates of which are connected to the (+) and (−) inputs, respectively, of an operational amplifier 18 of integrator 17. The (+) input conductor 26A of operational amplifier 18 is coupled by an integrating capacitor 24A to the (−) output conductor 27A of operational amplifier 18, and the (−) input conductor 26B of operational amplifier 18 is coupled by an integrating capacitor 24B to the (+) output conductor 27B of operational amplifier 18. Input conductor 26A is coupled by a sampling capacitor 28A to the pole of a single pole, triple throw switch circuit S1, and input conductor 26B is coupled by a sampling capacitor 28B to the pole of a single pole, triple throw switch circuit S2. Switch circuit S1 couples the (+) input of operational amplifier 18 through sampling capacitor 28A to Vref+, Vref− or an open terminal, depending upon whether the output CompOut of window comparator 30 is +1, −1, or 0, respectively, so the reference Vref can be integrated in the correct direction if necessary, depending on the decision of window comparator 30. Similarly, switch circuit S2 couples the (−) input of operational amplifier 18 through sampling capacitor 28B to Vref−, Vref+, or an open terminal, depending upon whether CompOut is +1, −1, or 0, respectively, so Vref can be integrated in the correct direction if necessary.
The output conductors 31 of window comparator 30 are coupled to the input of a digital filter 37, the output conductors 40 of which produce the basic un-corrected digital representation Dout of the input voltage Vin. The uncorrected signal Dout is multiplied by a digital gain correction coefficient by means of a digital multiplier 38 to produce a gain-corrected digital output signal Dout(gain-corrected).
FIG. 2 is a flowchart which indicates the operation of ADC 20A of FIG. 1. The part of FIG. 2 within dashed line A generally indicates how the delta-sigma modulator 15 consisting of integrator 17, window comparator 30, and switch circuits S1 and S2 operate in conjunction with window comparator 30 so as to cause the accumulation of new values in digital filter 37. As indicated in block 1 of FIG. 2, integrator 17 integrates only the input voltage Vin during the first integration cycle of delta-sigma modulator 15, since initially window comparator output CompOut is 0. Then, as indicated in block 2, window comparator 30 determines whether the output of integrator 17 is greater than a threshold voltage VTH+, less than VTH−, or between them. Depending on the results of this comparison, the output of window comparator 30 is “1”, “−1”, or “0”, respectively. The threshold voltages VTH+ and VTH− can be derived from Vref and the scaling of various capacitors in integrator 17 so as to provide the various desired window comparator threshold voltages VTH (not shown) of the standard comparators of which window comparator 30 is comprised.
In any case, window comparator output CompOut is coupled into and added to the accumulated result in digital filter 37. If modulator 15 is a first order delta-sigma modulator as shown in FIG. 1, digital filter 37 can be implemented as an up-down counter, i.e., as an accumulator. For first-order delta-sigma modulator 15 as shown in FIG. 1, the up-down counter or accumulator of digital filter 37 is incremented by 1 if the output of window comparator 30 is +1 as indicated in decision block 3 and block 4, is decremented by 1 if the output of window comparator 30 is −1 as indicated in decision block 5 and block 6, or remains unchanged if the output of window comparator 30 is “0” as indicated in block 7 of FIG. 2.
Then, as indicated in decision block 9, the process being performed in ADC 20A determines if all of the integration cycles required by ADC 20A have been performed. If this determination is negative, the integrate and compare loop including blocks 1-9 is repeated as needed to complete the basic analog-to-digital conversion. On the second and each following required integration cycle after the second, integrator 17 samples not only the input voltage Vin, but also samples the reference voltage value Vref+ or Vref− in accordance with window comparator output CompOut. In the case wherein CompOut is too high, i.e., the input to window comparator 30 is greater than the upper threshold voltage Vref−, window comparator 30 makes a decision to generate a +1 output level, and during the next integration cycle integrator 17 samples the lower reference voltage value VTH− in addition to sampling the input voltage Vin, and this causes the output of integrator 17 to decrease. Similarly, in the case wherein CompOut is too low, i.e., the input to window comparator 30 is less than the lower threshold voltage VTH−, window comparator 30 makes a decision to generate a −1 output level, and during the next integration cycle integrator 17 samples the upper reference voltage value VRef+ in addition to sampling the input voltage Vin, and this causes the output of integrator 17 to increase.
After the process of sampling Vin and Vref the required numbers of times, the determination of decision block 9 eventually is affirmative. The window comparator output CompOut then is coupled for the last time into digital filter 37, which then produces the uncorrected digital output Dout on bus 40, and the basic analog-to-digital conversion is complete.
After the basic conversion of Vin to the uncorrected digital output signal Dout on bus 40 has been completed, it is multiplied by a gain error trim coefficient to produce the corrected final digital output Dout(gain-corrected) of ADC 20A, as indicated in blocks 11, 12, and 13 in the flow chart of FIG. 2.
As an example, assume that an input voltage Vin of 1.0 volt and a reference voltage Vref are applied to ADC 20A of FIG. 1. Assume also that the analog-to-digital conversion of the applied 1.0 volt input signal is performed, and the result is not the desired 1.0 volt digital output voltage value, but instead is a 0.9 volt digital output voltage value because of gain error of ADC 20A. One way to correct the gain error in the digital domain is to determine the value of a digital gain correction coefficient, which in this simplified example is approximately 1.1, and store it in the ADC integrated circuit die. Then the digital output conversion value of 0.9 volt produced by digital filter 37 on bus 40 is automatically multiplied by the stored digital gain error trim coefficient of approximately 1.1. In this example of Vin being equal to 1.0 volt, the multiplication result is a corrected output value of Dout very close to 1 volt (actually, 0.99 volts). From then on, every time an analog to digital conversion of Vin is performed, the resulting digital output Dout on bus 40 is multiplied by the digital gain error trim coefficient 1.1 (in this simplified example) to thereby obtain a corrected digital output voltage Dout(gain-corrected).
A problem with the above described prior art technique is that implementing a digital multiplier is always expensive because it requires complex circuitry and a large amount of integrated circuit die area, and also because it requires a large amount of quiescent current and hence a large amount of power dissipation. The above described prior art technique also is very time-consuming, because the analog-to-digital conversion must be performed first, and then the slow digital multiplication of the ADC conversion result must be multiplied, bit by bit, by the digital error correction coefficient, which adds a substantial amount to the time required for the basic ADC conversion process in order to obtain a gain-error-corrected digital output value Dout(gain-corrected) which accurately represents Vin. An additional drawback of this digital multiplication process is the possibility that the ADC transfer function may have missing codes, due to round-off errors.
Another known digital technique for trimming ADC gain error is by changing the number of integration cycles in a first order delta sigma ADC. This method does not provide adequate trim resolution if the number of integration cycles is too low. (A 0.1% resolution change is often considered sufficient to be an acceptable increase in resolution order to achieve an acceptable ADC gain error correction.) In some ADC architectures, the number of integration cycles can be very low, so the resolution of the digital gain error correction is poor if the method of changing the number of integration cycles is used to accomplish the gain error correction. These architectures all have the problem that it is quite difficult to correct the ADC gain error by changing the number of samples.
Primary shortcomings of the prior art technique of multiplying the conversion result by a gain error correction coefficient are that it requires too much power dissipation and too much circuit complexity, and also requires too much chip area, and too much total analog-to-digital conversion time in order to obtain the gain-error-corrected digital output value.
Thus, there is an unmet need for an ADC which corrects its ADC transfer characteristic for gain error without increasing the amount of time required for obtaining a gain-corrected digital output substantially beyond the amount of time required for a basic analog to digital conversion.
There also is an unmet need for an ADC which corrects its ADC transfer characteristic for gain error without increasing the amount of integrated circuit chip area for obtaining a gain-corrected digital output substantially beyond the amount of chip area required for a basic analog to digital conversion.
There also is an unmet need for an ADC which corrects its ADC transfer characteristic for gain error without increasing the amount of power consumption required in obtaining a gain-corrected digital output substantially beyond the amount of power consumption required for a basic analog to digital conversion.
There also is an unmet need for an ADC which corrects its ADC transfer characteristic for gain error without the high level of circuit complexity generally associated with using analog circuit techniques to correct a transfer characteristic of an ADC for gain error.
There also is an unmet need for an ADC gain error correction technique which is particularly suitable for use in a delta-sigma/cyclic ADC architecture, and is also useful in a SAR ADC architecture and in a higher-order delta-sigma ADC architecture.